RISC-V CPU
WEBINAR SERIES
A RISC-V deep dive
Our expert speakers, who hold key leadership positions in the RISC-V community, are here to provide valuable insights into the architecture’s benefits and applications, helping you navigate its adoption with confidence.
Don’t miss this chance to learn from industry leaders and get your questions answered. Secure your interest and learn about each webinar below.
APXM-6200 Introduction
Speakers: Shreyas Derashri, VP of Compute, Imagination Technologies; Board Member of RISC-V International and RISE & Matt Bubis, Director of Product Management, Imagination Technologies
When: Thursday 20 June, 9:30AM
In this talk, you can learn about:
- The RISC-V standard, and why you should consider it for your next CPU
- Imagination’s experience in RISC-V development
- Whether Imagination’s new application processor, APXM-6200, is a good fit for your next project, with details on its performance, security solution and software offering.
Profiling and Debugging RISC-V Platforms
Speaker: Chris Owen, Senior Principal Software Engineer, Imagination Technologies
When: Friday 12 July, 4:30PM
Catapult SDK (providing build and debug tools) and the Catapult Studio extension pack for Visual Studio Code (providing an Integrated Development Environment) combine to form the best freely-available build, debug and profiling system for software development on a wide range of RISC-V platforms. They can be downloaded free from the Imagination website and from the Visual Studio Code marketplace.
In this live demonstration, users can find out how to get started using these tools and making use of all their features.
RISC-V Security and Global Platform TEE
Speaker: Nicholas Wood, Senior Principal Security Architect, Imagination Technologies; RISC-V International Security Horizontal Committee
When: Monday 22 July, 9:30AM
A CPU must deliver unimpeachable security so as to protect homes and businesses from malicious cyber activities, and to protect supply chains. In this talk you can learn:
- RISC-V’s approach to delivering on security
- How to deploy Global Platform TEE systems on APXM-6200 CPU and RISC-V architecture
- The security architecture of the Imagination APXM-6200 CPU
AI on RISC-V
Speaker: Kenneth Rovers, Senior Principle Hardware Architect, Imagination Technologies; Chair, RISC-V International Floating Point SIG
When: Friday August 9, 4:30PM
Nearly all devices of the future require the ability to run AI workloads performantly and efficiently. In this talk, you can learn:
- RISC-V’s approach to developing a competitive AI architecture
- AI-focused features within the RISC-V standard
- The AI capabilities of specific RISC-V CPUs
APXM-6200 Hardware Architecture
Speaker: Matt Bubis, Director of Product Management, Imagination Technologies and Ross Torkington, Senior Principal Hardware Engineer, Imagination Technologies
When: Wednesday August 14, 9:30AM
In this follow-on talk from the APXM-6200 Introduction, you can learn about the architectural design of APXM-6200, including:
- Interfaces
- Architectural features
- Fetch, Memory and Execute features
- Core complex architecture
- Security architecture
- Trace and debug architecture
- AI architecture
The RISC-V Software Ecosystem
Speaker: Simon Harvey, Director of Software Engineering, Imagination Technologies; RISE Technical Steering Committee
When: Thursday August 29, 4:30PM
No matter how impressive the performance numbers, hardware availability on its own isn’t sufficient; optimised software stacks are an essential component of a RISC-V solution. In this talk you can learn:
- RISC-V’s approach to delivering on software through projects including RISE.
- Update on progress made per software component
