Design optimisation kits to accelerate your time-to-market
Support for all stages of SoC and product development
In today’s SoC designs, the complexity and frequencies have steadily increased to meet the performance of the end-user demands while power budgets and SoC area are paramount for a solution to be competitive. Companies need validated synthesis, place-and-route, and signoff solutions that provide the flexibility to optimize for power, performance, or area (PPA) to best suit the target application for their heterogeneous processor implementations – from high-end GPU, AI, and automotive solutions down to the most power-sensitive of applications.
Significantly accelerate your time-to-market
We understand that the interaction between the physical properties of advanced technology nodes and the functionality of the IP is key if these ever-increasing targets are to be met. To enable licensees to get the very best results from our IP we have created a DOK™ (Design Optimization Kit) with each core, or family. With our DOKs, customers leveraging our IP can achieve improved quality of results, optimised to their specialist requirements, and reduce their all-important time to market.
Each DOK provides a comprehensive and immediate design implementation solution for our IP licensees that allows them to significantly accelerate time-to-market by removing the need for a lengthy design exploration phase. Your back end design team can hit the ground running on day one, leveraging all our expertise and design familiarity to drive your implementation forward without having to perform numerous iterations to learn the optimal placement and dataflow of our complex high performance IP cores.
Reference floorplans, and floorplan guidance, proven to achieve stated goals.
Fully deployable reference flows based on industry leading EDA software.
Documentation of the entire flow, including derivation of floorplan.
Training material/classes available either on-site or via the web.
Tailored advice for real-world use cases
The design points chosen in the generation of the DOK reflect genuine real-world use cases, the licensee can be assured that these targets are achievable without relying on specialist power-hungry standard cells, deep metal stacks, or extreme process corners. We only use readily available off-the-shelf cell IP and select our process corners and stacks based on typical customer feedback. More tailored advice to suit specific technology node choices and process points is available on request.
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