Key Features
Ultra-low latency
Low latency improves response time, which can be critical for saving lives on the road. When multiple cores are combined, they can all be dedicated to executing a single task, reducing latency and thus response time by a factor of eight.
Leading safety mechanisms
IMG Series4 incorporates IP-level safety features and is built using a design process that assists customers in achieving ISO 26262 certification. This enables functionally-safe neural network inference without compromising performance.
Stellar bandwidth efficiency
Imagination Tensor Tiling (ITT) efficiently packages up tensors into tiles, which are then processed in groups for which all the intermediate data is stored in local on-chip memory, minimising data transfers between layers of the network.
ADAS – Entry Level
Vehicles targeting L1 “feet free” style ADAS workloads, such as Cruise Control.
Data Centre
Graphics-rich applications such as cloud based gaming or content creation on data centre services where cost management is key.
Full Features & Specs
Headline Features
- Imagination Tensor Tiling
- Lossless weight compression
- Low latency
- High-density neural network acceleration
- Wide and variable bit-depth (4 to 16 bits)
- Dynamic fixed-point data type
- Per filter exponent selection
- Memory Management Unit
- Wide range of elementwise unit operations
- Embedded configurable on-chip memory
API support
- IMG DNN API
Framework Support
- Caffe
- TensorFlow
- ONNX
Bus interface
- AXI4
Memory system
- Virtual memory
TOPS
- 12.5 TOPS
MACs per clock rate
- 8-bit: 4096 MACs/clk per core
- 16-bit: 1024 MACS/clk per core
Imagination Tensor Tiling white paper
Our white paper, Imagination Tensor Tiling, will help you learn more about this critical bandwidth-saving technology in-depth, and provide insight into how it provides real-world benefits in our IMG Series4 NNA with key neural network models.
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