High-performance multi-gigabit networking solutions
ethernet abstract

Flexible. Configurable.

The multi-port Ethernet Packet Processor (EPP) family provides highly-configurable solutions that support multiple different configurations for routing and switching solutions. It combines hardware accelerators and a high-speed flexible DMA fabric to provide a complete, highly-optimised, yet flexible, hardware and software framework.
ethernet abstract

Router processor offload

Featuring hardware acceleration with integral processing capability onboard, the EPP family is a highly effective way of taking a significant load off the host processor, providing greater flexibility and choice over your CPU selection.
ethernet abstract

Advanced design

The EPP IP family utilises advanced design techniques to deliver optimum power and performance while maintaining consistent connectivity, complemented by a rich set of features.

Architectural advantages

The EPP architecture is suited to high-performance, low-power, low-silicon-area gateway SoCs.

It is composed of blocks, such as a QoS engine to achieve scalable and guaranteed performance. The routing IP offers functions such as packet classification, deep-packet inspection and modification, all programmable using multiple microprocessors. Hardware assists schedule and reorder packets to the programmable engines, while highly-programmable parallel, pattern-matching engines provide deep-packet inspection.

Blocks are connected using a proprietary bus for optimal throughput and highest performance with the smallest area. Separate busses provide data transfers and control packet communication for flexible performance that scales with internal memory and packet classification performance.

In concert with a host processor and a sub-system with peripherals such as a system controller, UART etc., the EPP can be used to design a complete SoC for multiple application use cases.

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