Imagination's Ethernet Packet Processor IP enables cutting-edge and power-efficient solutions for all forms of time-sensitive IP connectivity, zonal controllers, aggregators and automotive gateways; and all in the same highly-flexible and configurable engine.
Imagination's Ethernet Packet Processor IP enables flexible and high performance for various forms of data centre and industrial time-sensitive solutions for IP connectivity, in a highly-configurable, cutting-edge engine.
Router processor offload
The EPP architecture is suited to high-performance, low-power, low-silicon-area gateway SoCs.
It is composed of blocks, such as a QoS engine to achieve scalable and guaranteed performance. The routing IP offers functions such as packet classification, deep-packet inspection and modification, all programmable using multiple microprocessors. Hardware assists schedule and reorder packets to the programmable engines, while highly-programmable parallel, pattern-matching engines provide deep-packet inspection.
Blocks are connected using a proprietary bus for optimal throughput and highest performance with the smallest area. Separate busses provide data transfers and control packet communication for flexible performance that scales with internal memory and packet classification performance.
In concert with a host processor and a sub-system with peripherals such as a system controller, UART etc, the EPP can be used to design a complete SoC for multiple application use cases.
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