Reduced Instruction Set Computer (RISC)
What is RISC?
A reduced instruction set computer (RISC) architecture is a microprocessor which is designed with a small, highly optimised set of instructions, rather than a specialised set of instructions, as found in complex instruction set computer architectures (CISC). The instruction set of the computer is simplified to reduce the execution time: typically, only a single cycle is required to execute most of the instructions. The instruction length is generally fixed depending on whether it is 32-bit or 64-bit, and most operations are performed within the CPU registers. These characteristics are critical in cutting down the amount of hardware logic in silicon required, helping a RISC-V CPU to operate at high frequencies, meaning greater performance with lower power consumption. A complex instruction set computer (CISC) on the other hand, requires complex hardware to execute complex instructions resulting in higher power consumption. Code written for a RISC architecture is also simpler to test.
RISC-V is a modern interpretation of the RISC architecture, based on over 30 years of development experience. It is common, free, and open source, enabling software and hardware (processors) to be developed for it and, as an extension-based architecture, additional functionality can be added.
RISC compared to other architectures
Some CPUs have been created and designed to have a very small and very specific set of instructions. As their designs are quite different from the classic RISC design, they have been given other names. The most notable ones are MISC and TTA.
A MISC, or minimal instruction set computer, is a CPU in the form of a microprocessor, that contains a very small number of basic operations that form its instruction set. MISCs are usually stack-based, allowing for a smaller and faster decoding unit with fast operation of the individual instructions.
TTA or transport-triggered architecture is a type of processor design that programmes directly into the control of internal transport buses of a processor. TTA processors are built from independent function units and register files, which are connected by transport buses and sockets.
IMG CPU: Catapult
IMG CPU based on RISC-V ISA and designed for heterogenous solutions.
Imagination University Programme
Teaching materials include: RVfpga: Understanding Computer Architecture & RVFpga: Introduction to SoC Design.