RVfpga

Summary

Join Digi-Key for a close look at the inner workings of the RISC-V processor core and ways to implement a soft RISC-V processor core in a target (Xilinx) FPGA device. The RVfpga webinar covers the foundational knowledge that the next generation of Programmers and Engineers need to harness the potential of RISC-V. Digi-Key is proud to sponsor this webinar in collaboration with Imagination Technologies featuring Prof. Sarah Harris (UNLV). The webinar attendee will learn how to:

• Target a commercial RISC-V core and system-on-chip (SoC) to an FPGA
• Program the RISC-V SoC
• Add more functionality to the RISC-V SoC
• Analyze and modify the RISC-V core and memory hierarchy

After completing the RVfpga webinar, attendees will walk away with solid understanding of a commercial RISC-V processor, SoC, and ecosystem.

If you can’t attend the live webinar, be sure to still register as we’ll send you the recording afterward! This webinar will be in English only.

About the speaker

Dr Sarah L. Harris, Associate Professor of Electrical and Computer Engineering at the University of Nevada, Las Vegas

Dr Sarah L. Harris is an Associate Professor of Electrical and Computer Engineering at the University of Nevada, Las Vegas. She earned her M.S. and Ph.D. at Stanford University. Before joining UNLV in 2014, she was a faculty member at Harvey Mudd College from 2004-2014. She has also worked at Hewlett Packard, Nvidia, and the Technical University of Darmstadt and has collaborated with other companies including Southwest Research Institute, Intel, and Imagination Technologies. She is the co-author of three popular textbooks: Digital Design and Computer Architecture, 2nd Edition (2007), ARM Edition (2015), and RISC-V Edition (2021).

Dr Harris is also currently leading or co-leading two NSF-funded grants on Smart Cities and on integrating family support in STEM education. Her research interests include computer architecture and applications of embedded systems and machine learning to biomedical engineering and robotics.