The ideal single-core solution for NNA

Ultra-low latency

Low latency improves response time, which can be critical for saving lives on the road. When multiple cores are combined, they can all be dedicated to executing a single task, reducing latency and thus response time by a factor of eight.

Leading safety mechanisms

IMG Series4 incorporates IP-level safety features and is built using a design process that assists customers in achieving ISO 26262 certification. This enables functionally-safe neural network inference without compromising performance.

Stellar bandwidth efficiency

Imagination Tensor Tiling (ITT) efficiently packages up tensors into tiles, which are then processed in groups for which all the intermediate data is stored in local on-chip memory, minimising data transfers between layers of the network.

Full Features & Specs

Headline Features
  • Imagination Tensor Tiling
  • Lossless weight compression
  • Low latency
  • High-density neural network acceleration
  • Wide and variable bit-depth (4 to 16 bits)
  • Dynamic fixed-point data type
  • Per filter exponent selection
  • Memory Management Unit
  • Wide range of elementwise unit operations
  • Embedded configurable on-chip memory
API support
  • IMG DNN API
Framework Support
  • Caffe
  • TensorFlow
  • ONNX
Bus interface
  • AXI4
Memory system
  • Virtual memory
TOPS
  • 12.5 TOPS
MACs per clock rate
  • 8-bit: 4096 MACs/clk per core
  • 16-bit: 1024 MACS/clk per core

The leading dual-core solution for NNA

Ultra-low latency

Low latency improves response time, which can be critical for saving lives on the road. When multiple cores are combined, they can all be dedicated to executing a single task, reducing latency and thus response time by a factor of eight.

Leading safety mechanisms

IMG Series4 incorporates IP-level safety features and is built using a design process that assists customers in achieving ISO 26262 certification. This enables functionally-safe neural network inference without compromising performance.

Stellar bandwidth efficiency

Imagination Tensor Tiling (ITT) efficiently packages up tensors into tiles, which are then processed in groups for which all the intermediate data is stored in local on-chip memory, minimising data transfers between layers of the network.

Multi-core flexibility

Multi-core allows for flexible allocation and synchronisation of workloads across the cores. Imagination’s software, which provides fine-grained control and increases flexibility through batching, can now be exploited across any number of cores.

Full Features & Specs

Headline Features
  • Imagination Tensor Tiling
  • Lossless weight compression
  • Low latency
  • High-density neural network acceleration
  • Wide and variable bit-depth (4 to 16 bits)
  • Dynamic fixed-point data type
  • Per filter exponent selection
  • Memory Management Unit
  • Wide range of elementwise unit operations
  • Embedded configurable on-chip memory
API support
  • IMG DNN API
Framework support
  • Caffe
  • TensorFlow
  • ONNX
Bus interface
  • AXI4
Memory system
  • Virtual memory

 

TOPS
  • 25 TOPS
MACs per clock rate
  • 8-bit: 4096 MAC/clk per core
  • 16-bit: 1024 MAC/clk per core

The mega performance quad-core solution for NNA

Ultra-low latency

Low latency improves response time, which can be critical for saving lives on the road. When multiple cores are combined, they can all be dedicated to executing a single task, reducing latency and thus response time by a factor of eight.

Leading safety mechanisms

IMG Series4 incorporates IP-level safety features and is built using a design process that assists customers in achieving ISO 26262 certification. This enables functionally-safe neural network inference without compromising performance.

Stellar bandwidth efficiency

Imagination Tensor Tiling (ITT) efficiently packages up tensors into tiles, which are then processed in groups for which all the intermediate data is stored in local on-chip memory, minimising data transfers between layers of the network.

Multi-core flexibility

Multi-core allows for flexible allocation and synchronisation of workloads across the cores. Imagination’s software, which provides fine-grained control and increases flexibility through batching, can now be exploited across any number of cores.

Full Features & Specs

Headline Features
  • Imagination Tensor Tiling
  • Lossless weight compression
  • Low latency
  • High-density neural network acceleration
  • Wide and variable bit-depth (4 to 16 bits)
  • Dynamic fixed-point data type
  • Per filter exponent selection
  • Memory Management Unit
  • Wide range of elementwise unit operations
  • Embedded configurable on-chip memory
API support
  • IMG DNN API
Framework support
  • Caffe
  • TensorFlow
  • ONNX
Bus interface
  • AXI4
Memory system
  • Virtual memory
TOPS
  • 50 TOPS
MACs per clock rate
  • 8-bit: 4096 MAC/clk per core 
  • 16-bit:1024 MAC/clk per core

Key The super-high performance hexa-core solution for NNA

Ultra-low latency

Low latency improves response time, which can be critical for saving lives on the road. When multiple cores are combined, they can all be dedicated to executing a single task, reducing latency and thus response time by a factor of eight.

Leading safety mechanisms

IMG Series4 incorporates IP-level safety features and is built using a design process that assists customers in achieving ISO 26262 certification. This enables functionally-safe neural network inference without compromising performance.

Stellar bandwidth efficiency

Imagination Tensor Tiling (ITT) efficiently packages up tensors into tiles, which are then processed in groups for which all the intermediate data is stored in local on-chip memory, minimising data transfers between layers of the network.

Multi-core flexibility

Multi-core allows for flexible allocation and synchronisation of workloads across the cores. Imagination’s software, which provides fine-grained control and increases flexibility through batching, can now be exploited across any number of cores.

Full Features & Specs

Headline Features
  • Imagination Tensor Tiling
  • Lossless weight compression
  • Low latency
  • High-density neural network acceleration
  • Wide and variable bit-depth (4 to 16 bits)
  • Dynamic fixed-point data type
  • Per filter exponent selection
  • Memory Management Unit
  • Wide range of elementwise unit operations
  • Embedded configurable on-chip memory
API support
  • IMG DNN API
Framework Support
  • Caffe
  • TensorFlow
  • ONNX
Bus interface
  • AXI4
Memory system
  • Virtual memory
TOPS
  • 75 TOPS
MACs per clock rate
  • 8-bit: 4096 MAC/clk per core
  • 16-bit: 1024 MAC/clk per core

The ultra-high performance octa-core solution for NNA

Ultra-low latency

Low latency improves response time, which can be critical for saving lives on the road. When multiple cores are combined, they can all be dedicated to executing a single task, reducing latency and thus response time by a factor of eight.

Leading safety mechanisms

IMG Series4 incorporates IP-level safety features and is built using a design process that assists customers in achieving ISO 26262 certification. This enables functionally-safe neural network inference without compromising performance.

Stellar bandwidth efficiency

Imagination Tensor Tiling (ITT) efficiently packages up tensors into tiles, which are then processed in groups for which all the intermediate data is stored in local on-chip memory, minimising data transfers between layers of the network.

Multi-core flexibility

Multi-core allows for flexible allocation and synchronisation of workloads across the cores. Imagination’s software, which provides fine-grained control and increases flexibility through batching, can now be exploited across any number of cores.

Full Features & Specs

Features
  • Imagination Tensor Tiling
  • Lossless weight compression
  • Low latency
  • High-density neural network acceleration
  • Wide and variable bit-depth (4 to 16 bits)
  • Dynamic fixed-point data type
  • Per filter exponent selection
  • Memory Management Unit
  • Wide range of elementwise unit operations
  • Embedded configurable on-chip Memory
API support
  • IMG DNN API
Framework Support
  • Caffe
  • TensorFlow
  • ONNX
Bus interface
  • AXI4
Memory system
  • Virtual memory
TOPS
  • 100 TOPS
MACs per clock rate
  • 8-bit: 4096 MAC/clk per core
  • 16-bit: 1024 MAC/clk per core