Summary

Imagination is pleased to invite you to the second Cambridge RISC-V local chapter event, where Prof. Simon Moore from the University of Cambridge Department of Computer Science and Technology will introduce the principles and benefits of CHERI security on RISC-V.

CHERI security extensions to microprocessors fundamentally improve memory safety, which is the cause for 70% of all vulnerabilities in many software stacks (Microsoft systems, Google Chrome, etc.). Since 2010, University of Cambridge and SRI International have undertaken over 150 person years of research into refining the CHERI approach. Transitioning this research is being undertaken in part through the £200m Innovate UK Digital Security by Design program that includes the Morello evaluation platform from ARM Ltd (CHERI on ARM v8). Our work on CHERI for RISC-V provides an open-source solution and enabled Microsoft to produce their CHERI-RISC-V for IoT (CHERIoT) announced in February 2023.

This talk will introduce the principles and benefits of CHERI security. Opportunities and challenges of standardisation and wide-spread commercial deployment on RISC-V will be discussed. There will also be an opportunity to network with some of the CHERI team.

About the speaker

Simon Moore, Professor of Computer Engineering at the University of Cambridge.

Simon Moore is a Professor of Computer Engineering at University of Cambridge, Department of Computer Science and Technology (previously The Computer Laboratory) where he conducts research and teaching in the general area of computer architecture with particular interests in secure and rigorously-engineered processors and subsystems. Since 2010, he has led the microarchitecture work on CHERI for a number of ISAs including RISC-V. He is vice-chair of the CHERI special interest group at RISC-V International.